/*!
    \file    change log.txt
    \brief   change log for GD32A508 firmware

    \version 2025-08-08 V1.3.0, firmware for GD32A508
*/

/*
    Copyright (c) 2024, GigaDevice Semiconductor Inc.

    Redistribution and use in source and binary forms, with or without modification, 
are permitted provided that the following conditions are met:

    1. Redistributions of source code must retain the above copyright notice, this 
       list of conditions and the following disclaimer.
    2. Redistributions in binary form must reproduce the above copyright notice, 
       this list of conditions and the following disclaimer in the documentation 
       and/or other materials provided with the distribution.
    3. Neither the name of the copyright holder nor the names of its contributors 
       may be used to endorse or promote products derived from this software without 
       specific prior written permission.

    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
OF SUCH DAMAGE.
*/

******************* V1.2.0 2024-12-30 ******************************************************************************************
______________________Common______________________________________________________________________________________________
Fix file:
/fw3233/GD32A508_Firmware_Library/Firmware/CMSIS/GD/GD32A508/Source/system_gd32a508.c
fix reason:
frequence modify
V1.2.0:
none
V1.3.0:
                                
/* The following is to prevent Vcore fluctuations caused by frequency switching. 
   It is strongly recommended to include it to avoid issues caused by self-removal. */
#define RCU_MODIFY_UP(__delay)  do{                                     \
                                      volatile uint32_t i,reg;            \
                                      if(0 != __delay){                   \
                                          for(i=0; i<__delay; i++){       \
                                          }                               \
                                          reg = RCU_CFG0;                 \
                                          reg &= ~(RCU_CFG0_AHBPSC);      \
                                          reg |= RCU_AHB_CKSYS_DIV2;      \
                                          RCU_CFG0 = reg;                 \
                                          for(i=0; i<__delay; i++){       \
                                          }                               \
                                          reg = RCU_CFG0;                 \
                                          reg &= ~(RCU_CFG0_AHBPSC);      \
                                          reg |= RCU_AHB_CKSYS_DIV1;      \
                                          RCU_CFG0 = reg;                 \
                                      }                                   \
                                  }while(0)

______________________________________________________________________________________________________________________________



______________________USB____________________________________________________________________________________________

Fix file:
/fw3233/GD32A508_Firmware_Library/Firmware/GD32A508_usbhs_library/driver/Source/drv_usb_dev.c
fix reason:
Fix the issue where the enum_speed parameter may cause an array out-of-bounds error.

V1.2.0:
    uint8_t enum_speed = udev->regs.dr->DSTAT & DSTAT_ES;
V1.3.0:
    uint8_t enum_speed = ((udev->regs.dr->DSTAT & DSTAT_ES) >> 1U);
	

	
 Fix file:
/fw3233/GD32A508_Firmware_Library/Firmware/GD32A508_usbhs_library/device/core/Source/usbd_core.c
/fw3233/GD32A508_Firmware_Library/Firmware/GD32A508_usbhs_library/device/core/Source/usbd_enum.c
fix reason:
Modify the firmware library and pass the self-powered CVTest..

V1.2.0:
            } else {
                status[0] = 0U;
V1.3.0:
none
	
	
 Fix file:
/fw3233/GD32A508_Firmware_Library/Firmware/GD32A508_usbhs_library/driver/Source/drv_usbh_int.c
fix reason:
The out processing of the channel in the drv_usbh_int.c file of the host causes usb_pp_halt twice. Delete the redundant usb_pp_halt function.

V1.2.0:
        usb_pp_halt(udev, (uint8_t)pp_num, HCHINTF_NAK, PIPE_NAK);
V1.3.0:
none

__________________________________________________________________________________________________________________________

______________________CAN____________________________________________________________________________________________

Fix file:
/fw3233/GD32A508_Firmware_Library/Firmware/GD32A508_standard_peripheral/Source/gd32a508_can.c
fix reason:
When the number of bytes sent by CAN exceeds 8, the frame sent by CAN to the bus will have a problem.
Add a limit to the code, set to 8 when the number of bytes exceeds 8
V1.2.0:
NONE
V1.3.0:
        /* Classic CAN frame data length does not exceed 8 */
        if (transmit_message->tx_dlen > 8U) {
            transmit_message->tx_dlen = 8U;
        }
 
__________________________________________________________________________________________________________________________

______________________I2C____________________________________________________________________________________________

Fix file:
/fw3233/GD32A508_Firmware_Library/Firmware/GD32A508_standard_peripheral/Include/gd32a508_i2c.h
/fw3233/GD32A508_Firmware_Library/Firmware/GD32A508_standard_peripheral/Source/gd32a508_i2c.c
fix reason:
the configuration width of byte_number is 8 bit，the parameter can accept an input data width of 32 bits.
change the data type of byte_number from uint32_t to uint8_t
V1.2.0:
void i2c_transfer_byte_number_config(uint32_t i2c_periph, uint32_t byte_number)
V1.3.0:
void i2c_transfer_byte_number_config(uint32_t i2c_periph, uint8_t byte_number)

Fix file:
/fw3233/GD32A508_Firmware_Library/Firmware/GD32A508_standard_peripheral/Include/gd32a508_i2c.h
/fw3233/GD32A508_Firmware_Library/Firmware/GD32A508_standard_peripheral/Source/gd32a508_i2c.c
fix reason:
delete i2c_nack_disable, NACKEN not support clear by software. 
V1.2.0:
    \brief      generate an ACK in slave mode
    \param[in]  i2c_periph: I2Cx(x=2)
    \param[out] none
    \retval     none
*/
void i2c_nack_disable(uint32_t i2c_periph)
{
    I2C2_CTL1(i2c_periph) &= ~I2C2_CTL1_NACKEN;
}

/*!
V1.3.0:
NONE
 
__________________________________________________________________________________________________________________________

______________________USART_______________________________________________________________________________________________
Fix file:
/fw3233/GD32A508_Firmware_Library/Examples/USART/Half_duplex_transmitter&receiver/main.c
/fw3233/GD32A508_Firmware_Library/Examples/USART/Half_duplex_transmitter&receiver/readme.txt
fix reason: 
Modify TX pin to open-drain output
V1.2.0:
    /* configure the USART0 Tx pin and USART1 Tx pin */
    gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_9);
    gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_2);

V1.3.0:
    /* configure the USART0 Tx pin and USART1 Tx pin */
    gpio_init(GPIOA, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_9);
    gpio_init(GPIOA, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_2);
___________________________________________________________________________________________________________


______________________PMU____________________________________________________________________________________________

Fix file:
/fw3233/GD32A508_Firmware_Library/Firmware/GD32A508_standard_peripheral/Source/gd32a508_pmu.c
fix reason:
pmu_to_sleepmode MODIFY
V1.2.0:
void pmu_to_sleepmode(uint8_t sleepmodecmd)
{
    /* clear sleepdeep bit of Cortex-M33 system control register */
    SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);

    /* select WFI or WFE command to enter sleep mode */
    if(WFI_CMD == sleepmodecmd) {
        __WFI();
    } else {
        __WFE();
        __WFE();
    }
}
V1.3.0:
void pmu_to_sleepmode(uint8_t sleepmodecmd)
{
    /* clear sleepdeep bit of Cortex-M33 system control register */
    SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);

    /* select WFI or WFE command to enter sleep mode */
    if(WFI_CMD == sleepmodecmd) {
        __WFI();
    } else {
        __SEV();
        __WFE();
        __WFE();
    }
}
__________________________________________________________________________________________________________________________

______________________RTC_______________________________________________________________________________________________
Fix file:
/fw3233/GD32A508_Firmware_Library/Examples/RTC/Calendar_demo/main.c
fix reason: 
Add clear RCU_BDCTL_BKPRST flag
V1.2.0:
int main(void)
{
    /* COM0 configuration */
    gd_eval_com_init(EVAL_COM0);

    /* NVIC configuration */
    nvic_configuration();

    printf("\r\n This is a RTC demo...... \r\n");

    /* get RTC clock entry selection */
    RTCSRC_FLAG = GET_BITS(RCU_BDCTL, 8, 9);

    if((0xA5A5 != bkp_read_data(BKP_DATA_0)) || (0x00 == RTCSRC_FLAG)) {
        /* backup data register value is not correct or not yet programmed
        (when the first time the program is executed) */
        printf("\r\nThis is a RTC demo!\r\n");
        printf("\r\n\n RTC not yet configured....");

V1.3.0:
int main(void)
{
    /* COM0 configuration */
    gd_eval_com_init(EVAL_COM0);

    /* NVIC config */
    nvic_configuration();
    
    /* enable PMU and BKPI clocks */
    rcu_periph_clock_enable(RCU_BKPI);
    rcu_periph_clock_enable(RCU_PMU);
    /* allow access to BKP domain */
    pmu_backup_write_enable();
    if(RESET != (RCU_BDCTL & RCU_BDCTL_BKPRST)) {
        rcu_bkp_reset_disable();
    }
    
    /* get RTC clock entry selection */
    RTCSRC_FLAG = GET_BITS(RCU_BDCTL, 8, 9);

    printf( "\r\n This is a RTC demo...... \r\n" );

    if((0xA5A5 != bkp_read_data(BKP_DATA_0)) || (0x00 == RTCSRC_FLAG)) {
        /* backup data register value is not correct or not yet programmed
        (when the first time the program is executed) */
        printf("\r\nThis is a RTC demo!\r\n");
        printf("\r\n\n RTC not yet configured....");

___________________________________________________________________________________________________________


